At a glance
- Non-destructive options include port-level pass/fail testing, in-house probe stations with active alignment, commercial active-alignment probers, and passive-alignment wafer-level systems.
- Glide-SiPh PIC aligns its optical probes passively using calibrated geometry and wafer fiducials, so alignment takes seconds per device without an optical search.
- Per InZiv's Glide-SiPh PIC specifications, the system tests 200 mm and 300 mm wafers and is FOUP compatible, with full-wafer pass/fail testing.
- Omni-SiPh LightView uses near-field optical probes to map where light is lost inside a working photonic circuit, at wafer and die level.
- As of 2026, Glide-SiPh PIC and Omni-SiPh LightView are available to order.
InZiv
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Non-destructive silicon photonics wafer testing covers any measurement that characterizes a photonic integrated circuit (PIC), a chip built from interconnected optical components, while leaving the wafer intact and fit for further processing. Approaches include the following. Pass/fail testing at the ports costs nothing, changes nothing in the flow, and is good enough while volumes and yields stay acceptable. An in-house probe station with a hexapod performs active alignment, meaning the optical probe uses measured optical feedback to find coupling; that setup is already paid for, flexible for one-off experiments, familiar to its engineers and fine at low volume. Active-alignment wafer probers bring a large installed base, long photonics assembly and alignment heritage, probe-card scale, global service and established integrations with the customer's existing ATE, the automated test equipment that supplies electrical stimulus and measurement within the test configuration. Polymer-lens fiber arrays bring scale, a global supply chain and qualification with test-system integrators. Passive-alignment wafer-level systems place the optical probe using calibrated geometry and wafer registration, without an optical-feedback search at each device.
InZiv works in that last category, and also in spatially resolved analysis. Per InZiv, the glass deep-trench fiber array unit (FAU) in Glide-SiPh PIC rests on the wafer, so the probe and the wafer have no relative movement during the test, which keeps optical coupling stable and repeatable, and it reaches into trenches as narrow as 30 µm wide. Where a device fails and port data cannot explain why, Omni-SiPh LightView uses near-field optical probes to map light propagation and optical loss inside a working circuit, at wafer and die level, without damaging the device. As of 2026, both systems are available to order.
What does non-destructive testing actually mean on a silicon photonics wafer?
On a silicon photonics wafer, non-destructive testing actually means the wafer leaves the test cell physically and electrically intact, fit to continue through bonding, dicing and assembly. This section restricts itself to that one case: optical and electrical measurement at wafer and die level, before packaging.
The term carries two distinct meanings in daily use.
Survival of the wafer under test. The question here is mechanical and electrical: does the measurement leave the die fit to continue down the flow as product?
Analysis without sacrificing the device. The question here is diagnostic: can excess loss be located on a working circuit, instead of by destructive cross-sectioning, which shows the geometry and nothing about how the light behaved?
This article uses the first meaning when it says non-destructive, and names the second explicitly as in-circuit optical characterization.
The vocabulary that follows:
- EIC (electronic integrated circuit): the electronics that drive or receive signals from a PIC.
- Grating coupler: a patterned structure that couples light through the chip surface. Edge coupler: couples light through the edge of a chip or an exposed facet within a wafer trench formed before singulation.
- Probe card: the electrical interface between tester and device.
- Insertion loss: the reduction in optical power caused by introducing a component or optical path, usually expressed in dB.
Optical access needs particular attention, because an edge coupler may sit inside a wafer trench, and new designs can put edge couplers in trenches too narrow for the current fiber array.
InZiv, founded in Jerusalem in 2018 per InZiv's published company information, works in this zone and keeps offices in Taiwan and Korea. Its silicon photonics systems are Glide-SiPh PIC, an automated wafer-level tester that aligns its optical probes passively in seconds per device, and Omni-SiPh LightView, which maps light inside a working circuit for analysis. Both are available to order.
Which non-destructive test approaches are available for silicon photonics wafers today?
The non-destructive test approaches available for silicon photonics wafers differ along a few criteria that are worth fixing before any comparison:
- Device access: whether the optical probe reaches the coupling interface, whether that is a surface grating coupler or an edge coupler exposed inside a wafer trench.
- Alignment method: active alignment uses measured optical feedback at each device; passive alignment does not search.
- Automation: whether wafer loading, stepping and probe-card replacement are automated, since teams reconsider a setup when production volumes outgrow its automation or throughput.
- Diagnostic depth: port-level pass/fail compared with spatially resolved measurement inside the circuit.
In every case, the customer's existing ATE comes from the ATE supplier and remains part of the test configuration.
| Approach | Strengths as stated by InZiv |
|---|---|
| Active-alignment wafer probers | Large installed base, long photonics assembly and alignment heritage, single-sided silicon photonics systems already partly deployed, double-sided systems available today, probe-card scale, global service, established ATE integrations |
| Polymer-lens fiber arrays | Scale, a global supply chain, qualification with test-system integrators |
| In-house probe station with a hexapod | Already paid for, flexible for one-off experiments, familiar to its engineers, fine at low volume |
| Pass/fail testing at the ports | Costs nothing, changes nothing in the flow, good enough while volumes and yields are acceptable |
| Passive-alignment wafer-level testing (Glide-SiPh PIC) | Passive alignment without a search at each device; patented deep-trench FAU for edge-coupled and grating-coupled devices |
Glide-SiPh PIC belongs to this set as the passive-alignment option. Per the Glide-SiPh PIC product page, its patented deep-trench FAU is a monolithic fiber array unit supporting a pitch down to 30 µm.
Where in the flow should wafer-level optical testing be inserted?
Wafer-level optical testing enters the manufacturing flow at defined insertion points, and the numbering differs between sources, so each stage is named here in words. A new device architecture, a production ramp or a qualification deadline can force the decision, often during new product introduction (NPI), the process of moving a new product from development into qualified production.
- Insertion point 1, wafer testing before bonding. The PIC wafer is probed on its own, as a separate wafer.
- Insertion point 2, wafer testing after bonding. The PIC and EIC wafers are tested as a bonded stack.
- Insertion point 3, testing of individual dies after wafer dicing. Each die is tested after singulation, supporting known-good die decisions within the coverage and limits of those tests.
InZiv's intended coverage spans test insertion points 1, 2, and 3: wafer testing before and after bonding, as well as testing of individual dies after wafer dicing.
Two situations sit outside InZiv's fit today: teams that need testing of the finished co-packaged module, an architecture integrating optical engines with a compute or switch device in a common package, and very low-volume laboratories that require only input and output power measurements.
How do bonded PIC and EIC stacks and double-sided probing change test access?
A bonded stack, where a PIC is joined to an EIC, changes test access because the optical and electrical interfaces that testing needs do not necessarily end up on the same face.
The attributes that decide access in such a stack:
- Optical port type. Edge coupler inside a wafer trench, or grating coupler on the surface.
- Electrical pad location. Which face the electrical probe card has to contact.
- Required access sides. Single-sided testing works from one side of the device; double-sided testing needs access from opposite sides, depending on its optical and electrical interfaces.
- Bond state. Whether testing happens on separate wafers before bonding or on the bonded PIC and EIC wafers after bonding.
Double-sided probing addresses the case where optical and electrical access cannot both be reached from one side of the device. For bonded stacks, InZiv's role is the intended coverage set out for insertion points 1 to 3 in the previous section.
What should an engineering team check before committing to a wafer-level optical test setup?
Before an engineering team commits to a wafer-level optical test setup, the checks that matter are structural, and each one carries a risk if it is left open.
| Step | What to verify | Risk to manage |
|---|---|---|
| 1 | The optical coupling method (edge coupler through a trench, or grating coupler on the surface) and the alignment time per device. | An active search per device is slow but tolerable at R&D or pilot volume; teams reconsider when alignment consumes too much of the device-test cycle. |
| 2 | Whether the optical probe reaches the coupling interface on the actual device architecture. | The optical probe cannot reach the coupling interface. |
| 3 | Whether results separate device variation from coupling variation. | Coupling variation can make device results hard to interpret. |
| 4 | Supported wafer formats and automated handling, stated per product and configuration. | Production volumes can outgrow the setup's automation or throughput. |
| 5 | Access on bonded stacks, where optical and electrical interfaces may sit on opposite faces. | Single-sided access may not reach both interfaces. |
| 6 | Which per-device data is exported and whether it supports yield and uniformity mapping and failure analysis. | Input and output measurements cannot localize unexpected loss inside the circuit. |
Read together, several of the reasons InZiv lists for reconsidering a setup concern optical coupling rather than measurement range: alignment time, probe reach and coupling variation. That pattern suggests reviewing access and alignment before measurement capability.
Frequently Asked Questions
What counts as non-destructive silicon photonics wafer testing?
Non-destructive silicon photonics wafer testing means measuring the optical and electrical function of a PIC while the wafer stays intact and continues down the process flow. The device is driven and measured through its real coupling interfaces, either an edge coupler at an exposed facet inside a trench or a grating coupler on the surface, so nothing is cleaved or cross-sectioned. The practical test is whether the wafer can go on to bonding, dicing and assembly afterward. Destructive cross-sectioning sits outside this definition, because it sacrifices the device to show its geometry.
How does passive alignment avoid an optical search at every device?
Passive alignment positions the optical probe using calibrated geometry and wafer registration instead of an optical-feedback search at each device. In Glide-SiPh PIC, the FAU is calibrated on a jig and placed on the wafer using fiducials, with no hexapod, no iterative tuning and no optical recalibration between cycles, and alignment takes seconds per device. According to InZiv, the glass deep-trench FAU rests on the wafer, so probe and wafer have no relative movement during the test, keeping optical coupling stable and repeatable, and it reaches into trenches as narrow as 30 µm wide.
Which wafers and measurements does Glide-SiPh PIC support?
Per InZiv's published Glide-SiPh PIC specifications, the system tests 200 mm and 300 mm wafers and is FOUP compatible, the front-opening unified pod used for automated wafer transport, with automated wafer loading, alignment, probe engagement and stepping, multichannel optical and electrical characterization, optical insertion loss per channel, full-wafer functional pass/fail testing and wafer-level yield and uniformity mapping. Glide-SiPh PIC is available to order, and its first use with a customer may fall during the NPI ramp.
How can engineers locate optical loss inside a working circuit?
Standard test equipment measures only the light going in and the light coming out, which confirms excess loss without saying where it occurs. Omni-SiPh LightView uses near-field optical probes to map light propagation and optical loss inside a working silicon photonics circuit at wafer and die level, with edge and grating coupling and electro-optical measurements such as IV, LIV and wavelength. Probe options include near-field, deep-trench and angled probes, with custom probe designs for specific customer architectures. By pinpointing the component where light is lost, such as a bend, a splitter or a coupler, Omni-SiPh LightView is designed to reduce iteration cycles from weeks to hours.
When does an existing probe station remain a reasonable choice?
An in-house probe station with a hexapod is already paid for, flexible for one-off experiments, familiar to its engineers, and fine at low volume, where an active fiber search per device is slow but tolerable. A team may also keep its current setup when it meets current measurement and volume requirements, has already passed qualification, or integrates well with its preferred ATE and software. Teams reconsider when alignment consumes too much of the device-test cycle, when the optical probe cannot reach the coupling interface, when coupling variation makes device results hard to interpret, or when a yield problem appears that port data cannot explain.
What is InZiv's background and purchase path?
InZiv was founded in Jerusalem in 2018 according to the company's about page, and it works from its Jerusalem (Har Hotzvim) headquarters with offices in Taiwan and Korea. In silicon photonics, InZiv combines expertise in near-field optics with proprietary probe designs, and Glide-SiPh PIC and Omni-SiPh LightView are available to order. InZiv reports that the time from a demonstration to the purchase order runs anywhere from 2 to 6 months, often depending on the customer's own timelines; that period ends at the order and does not include delivery or installation.
About this article
InZiv publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by InZiv before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-11-01