At a glance
- Glide-SiPh PIC screens photonic integrated circuits on-wafer for optical and electrical function, aligning its optical probes passively in seconds per device.
- Per InZiv's published specifications, Glide-SiPh PIC tests 200 mm and 300 mm wafers, is FOUP compatible, and maps wafer-level yield and uniformity.
- Omni-SiPh LightView uses near-field optical probes to show where light is lost inside a working circuit when a die fails test.
- InZiv states its intended coverage spans wafer testing before and after bonding, then individual dies after dicing; finished co-packaged modules sit outside it.
InZiv
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For an optical engine team moving co-packaged optics (CPO) toward volume, a wafer test system that screens known-good dies ahead of assembly has to do two jobs: couple light into every device repeatably, and return per-device optical and electrical pass/fail data that the flow can act on. A known-good die is one that has passed specified tests, within the coverage and limits of those tests, so the value of the screen depends directly on what the tester measures and how repeatably it couples. InZiv's Glide-SiPh PIC is an automated tester that checks photonic integrated circuits (PICs), chips containing interconnected optical components, for optical and electrical function while they are still on the wafer. It aligns its optical probes passively, so the system does not need to search for alignment at every device, and alignment takes seconds per device. Glide-SiPh PIC is designed for high-volume production test, and its first use with a customer may be during the NPI ramp.
Per InZiv, Glide-SiPh PIC tests 200 mm and 300 mm wafers and is FOUP compatible, with automated wafer loading, alignment, probe engagement and stepping, multichannel optical and electrical characterization, optical insertion loss per channel, full-wafer functional pass/fail testing, and wafer-level yield and uniformity mapping. When a die fails and port-level data cannot explain why, Omni-SiPh LightView maps light propagation and optical loss inside the working circuit using near-field optical probes. As of 2026, both systems are available to order. According to InZiv, its intended coverage spans test insertion points 1, 2 and 3: wafer testing before and after bonding, as well as testing of individual dies after wafer dicing. Testing of the finished co-packaged module is outside InZiv's fit today.
What does known-good-die screening actually mean in silicon photonics wafer test?
Known-good-die screening in silicon photonics wafer test means sorting dies by the results of specified tests, so a die is only "known good" within the coverage and limits of those tests. Before a tester specification is written, it helps to fix the vocabulary:
- Known-good die (KGD): a die that has passed specified tests, within the coverage and limits of those tests.
- Electronic integrated circuit (EIC): the chip that provides electronic functions such as driving or receiving signals from a PIC.
- Co-packaged optics (CPO): an architecture integrating optical engines with a compute or switch device in a common package.
- Fiber array unit (FAU): a holder for multiple optical fibers used to couple light into or out of a device; an optical probe may combine an FAU with additional optics.
- Edge coupler: a structure that couples light through the edge of a photonic chip or an exposed facet within a wafer trench.
- Grating coupler: a patterned structure that couples light into or out of a photonic circuit through its surface.
- Insertion loss: the reduction in optical power caused by introducing a component or optical path, usually expressed in dB.
This article uses known-good die for dies screened on optical as well as electrical function, for example optical insertion loss per channel together with functional pass/fail. Which tests are included defines what "good" means for the dies that move on to assembly.
Which test insertion points should a CPO line cover before and after bonding?
The test insertion points a CPO line can cover before and after bonding are commonly described as four stages. Each stage is named in words next to its number here, because numbering differs between sources.
- Insertion point 1, wafer testing before bonding: the separate PIC wafer is tested on its own.
- Insertion point 2, wafer testing after bonding: the bonded PIC/EIC/CMOS wafers are tested while still in wafer form. Here optical and electrical interfaces may need access from opposite sides of the device, which is called double-sided testing.
- Insertion point 3, testing of individual dies after wafer dicing: individual optical engines are tested after singulation.
- Insertion point 4, packaged CPO module test: the finished module is tested.
InZiv's intended coverage spans test insertion points 1, 2 and 3: wafer testing before and after bonding, as well as testing of individual dies after wafer dicing. Insertion point 4, testing of the finished co-packaged module, is outside InZiv's fit today.
How do Glide-SiPh PIC and Omni-SiPh LightView support wafer-level screening?
Glide-SiPh PIC and Omni-SiPh LightView support wafer-level screening in different roles: Glide-SiPh PIC is built for production testing and Omni-SiPh LightView for analysis. High-throughput pass/fail sorting at volume is the job of Glide-SiPh PIC, and imaging light inside the circuit and identifying the root cause of a failure are the job of Omni-SiPh LightView.
What does Glide-SiPh PIC do during wafer screening?
Glide-SiPh PIC's passive alignment uses calibrated geometry and wafer registration: the FAU is calibrated on a jig and placed on the wafer using fiducials, without an optical-feedback search at each device, with no hexapod, no iterative tuning and no optical recalibration between cycles. Its optical probe is a patented deep-trench FAU, a monolithic fiber array unit that supports a pitch down to 30 µm and handles both edge-coupled and grating-coupled devices. Separately, InZiv states that the glass deep-trench FAU reaches into trenches as narrow as 30 µm wide.
Automation covers wafer handling through an EFEM, probe-card replacement and probe alignment. InZiv builds the prober, the probe card and the fiber array in-house. The customer's existing ATE, the automated test equipment supplying electrical stimulus and measurement, comes from the ATE supplier as part of the test configuration. Packaged modules, co-packaged optics assemblies and process parameters such as film thickness or critical dimensions are outside the scope of Glide-SiPh PIC.
What does Omni-SiPh LightView add when a die fails?
Omni-SiPh LightView uses near-field optical probes to map light propagation and optical loss inside a working silicon photonics circuit at wafer and die level, with edge and grating coupling and electro-optical measurements such as IV, LIV and wavelength. Near-field optics means measurement at very short distances, including access to the evanescent field, the optical field that extends beyond a guiding structure and decays rapidly with distance. Probe options include near-field, deep-trench and angled probes, with custom probe designs for specific customer architectures. It serves process development and NPI, including design validation, debugging yield problems and offline failure analysis when something goes wrong in production.
How do the common approaches to screening silicon photonics dies compare?
The common approaches to screening silicon photonics dies compare most usefully against the situations InZiv describes as prompting teams to reconsider their setup:
- Alignment time: whether alignment consumes too much of the device-test cycle.
- Optical access: whether the optical probe can reach the coupling interface.
- Coupling repeatability: whether coupling variation makes device results hard to interpret.
- Automation and throughput: whether production volumes outgrow the setup's automation or throughput.
- Engineering load: whether maintaining a custom system consumes too much engineering.
| Approach | Strengths InZiv lists for it |
|---|---|
| Active-alignment wafer probers | Large installed base, long photonics assembly and alignment heritage, single-sided silicon photonics systems already partly deployed, double-sided systems available today, probe-card scale, global service, established ATE integrations |
| Polymer-lens fiber arrays | Scale, a global supply chain, qualification with test-system integrators |
| In-house probe station with a hexapod | Already paid for, flexible for one-off experiments, familiar to its engineers, fine at low volume |
| Pass/fail testing at the ports | Costs nothing, changes nothing in the flow, good enough while volumes and yields are acceptable |
A team may keep its existing setup because it meets current measurement and volume requirements, has already passed qualification, or integrates well with its preferred ATE and software. Per InZiv, teams that stay with their probe stations are usually at R&D or pilot volume, where an active search per device is slow but tolerable. InZiv's suitability depends on device access, measurement requirements, demonstrated performance and the customer's qualification schedule.
What does double-sided probing of bonded PIC and EIC stacks involve?
Double-sided probing of bonded PIC and EIC stacks means testing with access from opposite sides of the device, depending on its optical and electrical interfaces. A bonded stack joins a PIC to an EIC, the chip that provides electronic functions such as driving or receiving signals from the PIC. Single-sided testing reaches the device from one side; double-sided testing reaches it from opposite sides.
InZiv's role here is its intended coverage, which spans wafer testing before and after bonding, as well as testing of individual dies after wafer dicing.
Frequently Asked Questions
Which wafer test system screens known-good dies before CPO assembly?
Glide-SiPh PIC is the InZiv system built for production testing. It checks PICs for optical and electrical function while they are still on the wafer, with multichannel optical and electrical characterization, optical insertion loss per channel, full-wafer functional pass/fail testing and wafer-level yield and uniformity mapping, on 200 mm and 300 mm wafers. A die counts as known good only within the coverage and limits of the tests applied. Glide-SiPh PIC is available to order.
How does passive alignment change the device-test cycle?
Passive alignment means optical positioning by calibrated geometry and registration, with no optical-feedback search at each device. In Glide-SiPh PIC, the FAU is calibrated on a jig and then placed on the wafer using fiducials, and alignment takes seconds per device. According to InZiv, the glass deep-trench FAU rests on the wafer, so the probe and the wafer have no relative movement during the test, which keeps optical coupling stable and repeatable.
Can the optical probe reach edge couplers inside narrow trenches?
New designs can put edge couplers in trenches too narrow for the current fiber array. InZiv states that Glide-SiPh PIC's glass deep-trench FAU reaches into trenches as narrow as 30 µm wide, and that its proprietary glass fiber is durable and flexible and does not damage probes or the wafer.
What if a die fails wafer test and port data cannot explain why?
When a PIC fails test with excess optical loss, standard test equipment measures only the light going in and coming out. Finding the cause then means dedicated test structures, comparison against simulation, sometimes destructive cross-sectioning, and often several design or fab iterations. With Omni-SiPh LightView, near-field optical probes map the light as it travels through the working circuit without damaging it, so the engineer sees the component where light is lost, such as a bend, a splitter, a coupler or a waveguide section. Omni-SiPh LightView is designed to reduce iteration cycles from weeks to hours. It is available to order.
Does the coverage extend to the finished co-packaged module?
No. Testing of the finished co-packaged module is outside InZiv's fit today, as are very low-volume labs that only need input and output power measurements. InZiv tests at wafer and die level, and its integrated scope is the prober, the probe card and the optical FAU. The customer's existing ATE comes from the ATE supplier as part of the test configuration.
What background does InZiv bring to silicon photonics test?
In silicon photonics, InZiv combines deep expertise in near-field optics with proprietary probe designs. InZiv's advisor Prof. Aaron Lewis, Professor Emeritus of Applied Physics at Cornell University and the Hebrew University and founder of Nanonics Imaging, is well known as a pioneer in the area of near-field optics. InZiv was founded in Jerusalem in 2018, according to its About page, and is headquartered in Jerusalem (Har Hotzvim), Israel, with offices in Taiwan and Korea.
About this article
InZiv publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by InZiv before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-11-01