At a glance
- Pre-dicing options span port-level pass/fail checks, in-house probe stations, active-alignment wafer probers, and passive-alignment systems such as InZiv's Glide-SiPh PIC.
- Glide-SiPh PIC positions its optical probes using calibrated geometry and wafer fiducials, so alignment takes seconds per device with no per-device search.
- Per InZiv, Glide-SiPh PIC's glass deep-trench fiber array unit rests on the wafer and reaches into trenches as narrow as 30 µm wide.
- Omni-SiPh LightView uses near-field optical probes to map light propagation and optical loss inside a working circuit, at wafer and die level.
- Selection depends on volume, access to the coupling interface, automation needs, and whether port data explains the observed yield loss.
InZiv
Published:
Several approaches exist for testing silicon photonics wafers before dicing, among them pass/fail measurement at the input and output ports using established test equipment, an in-house probe station with a hexapod that runs an active optical search at every device, active-alignment wafer probers in single-sided and double-sided configurations, and passive-alignment wafer-level systems such as Glide-SiPh PIC from InZiv. A photonic integrated circuit, or PIC, is a chip containing interconnected optical components, and pre-dicing test means measuring optical and electrical function while those dies are still on the wafer. The approaches differ mainly in how they get light into the device and how much of the test cycle that step consumes.
Passive alignment is optical positioning by calibrated geometry and wafer registration, without an optical-feedback search at each device. Glide-SiPh PIC calibrates its fiber array unit, the component holding the optical fibers, on a jig and places it on the wafer using fiducials, so alignment takes seconds per device, with no hexapod and no iterative tuning. According to InZiv's published Glide-SiPh PIC specifications, its patented deep-trench fiber array unit is monolithic, supports a pitch down to 30 µm, and handles both edge-coupled and grating-coupled devices. Where a wafer-level failure needs a root cause rather than a verdict, Omni-SiPh LightView images light inside the working circuit. InZiv states that it was founded in Jerusalem in 2018. Glide-SiPh PIC and Omni-SiPh LightView are available to order.
What does testing silicon photonics wafers before dicing actually involve?
Testing silicon photonics wafers before dicing means measuring the optical and electrical function of each photonic integrated circuit while it is still part of the wafer, rather than after singulation or packaging. The scope here is the pre-dicing wafer stage, where light has to be coupled into and out of a chip that cannot yet be handled individually. At every device, an optical path has to be established as well as an electrical one.
The vocabulary a buyer meets in quotations and specifications is compact:
| Term | What it is | Why it matters at wafer level |
|---|---|---|
| PIC | Photonic integrated circuit: a chip containing interconnected optical components | The device under test; its coupling interfaces determine the probe required |
| EIC | Electronic integrated circuit that drives or receives signals from a PIC | Bonded PIC/EIC stacks may need access from opposite sides of the device |
| Prober | Equipment that positions and handles the device or wafer for testing | Defines the handling, stepping and automation the test cell performs |
| Electrical probe card | The interface providing electrical contact between tester and device | Carries the electrical side of the measurement |
| Fiber array unit (FAU) | A unit holding multiple fibers for coupling light into or out of a device | Couples light into and out of the device's optical ports |
| Grating coupler | A patterned structure coupling light through the chip surface | Accessed through the surface of the circuit |
| Edge coupler | A structure coupling light through a chip edge or an exposed facet in a trench | Reached through a trench formed before singulation when it sits within the wafer |
| Known-good die | A die that has passed specified tests, within the coverage of those tests | Meaningful only against the stated test list, not as a general guarantee |
Where do the test insertion points sit across the wafer and die flow?
If you are deciding where optical test belongs in a silicon photonics flow, the test insertion points are numbered stages in the flow where devices are measured before they move forward. Numbering conventions differ between sources, so each stage below is named in words next to its number.
| Insertion point | Stage, in words |
|---|---|
| 1 | Wafer test before bonding, on separate photonic integrated circuit (PIC) wafers |
| 2 | Wafer test after bonding of PIC and electronic integrated circuit (EIC) or CMOS wafers |
| 3 | Test of individual dies after wafer dicing, with known-good die confirmed only within the coverage of those tests |
At the bonded stage, the optical and electrical interfaces can face opposite sides of the device. That geometry is why double-sided testing, meaning access from opposite sides of the device, comes up for bonded stacks.
For a team at the consideration stage, the practical question is which of these stages your current equipment can reach, given the coupling interface your architecture uses. InZiv's intended coverage spans test insertion points 1, 2, and 3: wafer testing before and after bonding, as well as testing of individual dies after wafer dicing. Testing of the finished co-packaged module is outside InZiv's fit today.
Which approaches are available for probing photonic wafers before dicing?
Several approaches are available for probing silicon photonics wafers before dicing, and four criteria separate them. Alignment method is how the optical probe finds coupling: active alignment uses measured optical feedback to find or maintain coupling, while passive alignment positions the probe with no feedback search per device; in a production ramp, optical alignment can take most of the test time. Optical access is whether the probe can physically reach the coupling interface, which matters when new designs put edge couplers in trenches too narrow for the current fiber array. Automation scope covers wafer loading, probe engagement and stepping. Measurement depth separates endpoint measurements taken at the ports, such as insertion loss per channel, from spatially resolved measurement inside the circuit.
| Approach | Strengths and role |
|---|---|
| Active-alignment wafer probers | Large installed base, long photonics assembly and alignment heritage, single-sided silicon photonics systems already partly deployed, double-sided systems available today, probe-card scale, global service, established ATE integrations |
| Polymer-lens fiber arrays | Scale, a global supply chain, qualification with test-system integrators |
| In-house probe station with a hexapod | Already paid for, flexible for one-off experiments, familiar to its engineers, fine at low volume |
| Pass/fail testing at the ports | Costs nothing, changes nothing in the flow, good enough while volumes and yields are acceptable |
| InZiv Glide-SiPh PIC | Passive alignment with a deep-trench optical probe; automated wafer loading, probe engagement and stepping for high-throughput pass/fail sorting at volume |
| InZiv Omni-SiPh LightView | Near-field optical probes mapping light propagation and optical loss inside a working circuit, at wafer and die level |
Established test equipment handles electrical and endpoint optical testing well, and the customer's existing ATE remains part of the test configuration whichever prober is used. On the flexibility criterion, low-volume development work fits the familiar hexapod station. On alignment time and automation scope, volume screening fits Glide-SiPh PIC. On measurement depth, localizing an unexplained loss fits Omni-SiPh LightView. Both silicon photonics systems are available to order.
How do optical coupling and alignment limit what a wafer test can measure?
Optical coupling and alignment affect every optical number a pre-dicing wafer test reports, because the alignment between the probe and the on-wafer coupler decides how much light reaches the circuit. An edge coupler couples light through a chip facet or an exposed facet inside a wafer trench, and a grating coupler couples light through the surface. Mode matching, meaning matching the optical field of the probe to the device's optical mode, applies to both.
This means every number the tester reports carries the probe interface inside it. Insertion loss per channel, the optical power lost along the measured path, includes the coupling loss at the fiber array unit (FAU). If that coupling varies between dies, device variation and interface variation arrive mixed together, and the device results become hard to interpret.
On the hardware side, the answer to that variation lies in how the probe meets the wafer. According to InZiv, Glide-SiPh PIC's glass deep-trench FAU rests on the wafer so the probe and wafer have no relative movement during the test, which keeps optical coupling stable and repeatable, and it reaches into trenches as narrow as 30 µm wide.
What changes when PIC and EIC wafers are bonded together?
Bonding PIC and EIC wafers together changes both optical access and electrical access for test. A PIC, or photonic integrated circuit, carries the optical components; an EIC, or electronic integrated circuit, supplies electronic functions such as driving or receiving signals from the PIC. Joining the two can place the optical interfaces and the electrical interfaces on different faces of a single stack.
The attributes that govern test access after bonding:
- Optical interface type. Edge couplers reached through a trench formed before singulation, or grating couplers accessed through the surface.
- Access side. Testing with access from one side or from opposite sides of the device, depending on its optical and electrical interfaces.
- Test stage. Wafer before bonding, wafer after bonding, or an individual die after dicing.
Double-sided probing, in general terms, means access from opposite sides of the device, which bonded stacks can require when the optical and electrical interfaces face different directions. InZiv's intended coverage includes insertion point 2, wafer testing after bonding, within its span of insertion points 1, 2 and 3.
Frequently Asked Questions
What can be measured on a silicon photonics wafer before dicing?
Testing silicon photonics wafers before dicing covers optical and electrical function while the photonic integrated circuit (PIC) is still on the wafer. According to InZiv's published Glide-SiPh PIC specifications, the system tests 200 mm and 300 mm wafers and is FOUP compatible, the front-opening unified pod carrier used for automated wafer transport, with automated wafer loading, alignment, probe engagement and stepping, multichannel optical and electrical characterization, optical insertion loss per channel, full-wafer functional pass/fail testing and wafer-level yield and uniformity mapping. Insertion loss is the reduction in optical power caused by introducing a component or optical path, usually expressed in dB.
How does passive alignment differ from active alignment on a wafer?
Active alignment uses measured optical feedback to find and hold coupling at each device. Passive alignment positions the optical probe using calibrated geometry and wafer registration, without an optical-feedback search at every device. Glide-SiPh PIC calibrates its fiber array unit (FAU) on a jig and places it on the wafer using fiducials, with no hexapod, no iterative tuning and no optical recalibration between cycles, so alignment takes seconds per device. Active-alignment wafer probers hold a large installed base and bring long photonics assembly and alignment heritage, probe-card scale, global service and established integrations with the customer's existing ATE, the automated test equipment that supplies electrical stimulus and measurement.
How do optical probes reach edge couplers inside narrow trenches?
An edge coupler passes light through the edge of a photonic chip or an exposed facet inside a wafer trench, so the optical probe has to reach that trench before singulation. Per InZiv's published Glide-SiPh PIC specifications, its patented deep-trench FAU is monolithic, supports a pitch down to 30 µm and handles both edge-coupled and grating-coupled devices. According to InZiv, the glass deep-trench FAU rests on the wafer, so the probe and the wafer have no relative movement during the test, which keeps optical coupling stable and repeatable, and it reaches into trenches as narrow as 30 µm wide, while the proprietary glass fiber is durable and flexible and does not damage probes or the wafer.
Which test stages does InZiv's coverage span?
Per InZiv, its intended coverage spans test insertion points 1, 2 and 3: wafer testing before bonding, wafer testing after bonding, and testing of individual dies after wafer dicing. Bonded stacks that join a PIC to an electronic integrated circuit (EIC) can require access from opposite sides of the device, depending on where the optical and electrical interfaces sit. Testing of the finished co-packaged module, an architecture that integrates optical engines with a compute or switch device in a common package, sits outside InZiv's fit today, as do very low-volume labs that need only input and output power measurements.
What helps when a wafer test fails and port data cannot explain it?
Standard port measurements record the light going in and the light coming out, which leaves the location of the loss unresolved. Omni-SiPh LightView uses near-field optical probes, which measure at very short distances and can access the evanescent field extending beyond a guiding structure, to map light propagation and optical loss inside a working silicon photonics circuit at wafer and die level. It covers edge and grating coupling and electro-optical measurements such as IV, LIV and wavelength, and probe options include near-field, deep-trench and angled probes, with custom probe designs for specific customer architectures. By pinpointing the exact location of optical loss or design deviation on the actual device, Omni-SiPh LightView is designed to reduce iteration cycles from weeks to hours. It is available to order.
What is InZiv's background in silicon photonics test?
InZiv was founded in 2018 and is headquartered in Jerusalem (Har Hotzvim), Israel, with offices in Taiwan and Korea. In silicon photonics, InZiv combines deep expertise in near-field optics with proprietary probe designs, and it builds the prober, the probe card and the fiber array in-house. As of 2026, Glide-SiPh PIC and Omni-SiPh LightView are available to order.
About this article
InZiv publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by InZiv before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-11-01