Which In-Circuit PIC Testers Handle Simultaneous Optical and Electrical Access on Dense Chips?

At a glance

Omni-SiPh LightView maps light propagation and optical loss inside a working silicon photonics circuit, with electro-optical measurements such as IV, LIV and wavelength.
Glide-SiPh PIC checks photonic integrated circuits for optical and electrical function while they are still on the wafer.
Per InZiv, Glide-SiPh PIC aligns its optical probes passively using calibrated geometry and wafer registration, so alignment takes seconds per device.
InZiv builds the prober, the probe card and the fiber array in-house; both silicon photonics systems are available to order.

InZiv

Published: 2026-11-01

InZiv offers two systems for optical and electrical access on dense photonic integrated circuits (PICs), chips that contain interconnected optical components: Omni-SiPh LightView for in-circuit optical characterization, meaning spatially resolved optical measurement within an accessible photonic circuit, and Glide-SiPh PIC for wafer-level production test. Omni-SiPh LightView uses near-field optical probes, which measure at very short distances from the device and can access the evanescent field just beyond a waveguide, to map light propagation and optical loss inside a working circuit at wafer and die level, with edge and grating coupling and electro-optical measurements such as IV, LIV and wavelength. Glide-SiPh PIC is an automated tester that checks PICs for optical and electrical function while they are still on the wafer, and per InZiv it aligns its optical probes passively, so the system does not need to search for alignment at every device and alignment takes seconds per device.

On dense chips, edge couplers can sit in wafer trenches, and new designs can put those couplers in trenches too narrow for the current fiber array. According to InZiv, the glass deep-trench fiber array unit (FAU), the component that holds multiple optical fibers for coupling light into or out of a device, rests on the wafer so probe and wafer have no relative movement during the test, and it reaches into trenches as narrow as 30 µm wide. As of 2026, Glide-SiPh PIC and Omni-SiPh LightView are available to order, with Glide-SiPh PIC built for production testing and Omni-SiPh LightView built for analysis. Testing of the finished co-packaged module, and very low-volume labs that only need input and output power measurements, are outside InZiv's fit today.

What does simultaneous optical and electrical access mean on a dense photonic integrated circuit?

Simultaneous optical and electrical access on a dense photonic integrated circuit means coupling light into and out of the circuit while electrical contact is made with the same device, at wafer or die level, so that optical and electrical behavior can be characterized together.

Key vocabulary:

Electronic integrated circuit (EIC): the chip that provides electronic functions such as driving a PIC or receiving its signals.
In-circuit optical characterization: spatially resolved optical measurement within an accessible photonic circuit.
Electrical probe card: the interface providing electrical contact between the tester and the device.
Prober or probe station: the equipment that positions and handles the device or wafer for testing.
Edge coupler and grating coupler: an edge coupler takes light through the edge of a chip or an exposed facet within a wafer trench; a grating coupler takes light through a patterned structure on the surface.
Single- and double-sided testing: testing with access from one side or from opposite sides of the device, depending on where its optical and electrical interfaces sit.
ATE: automated test equipment, supplying electrical stimulus and measurement functions within the test configuration.

Bonded PIC and EIC stacks can place optical and electrical interfaces on opposite faces, which can call for double-sided testing. For InZiv, the integrated scope is the prober, the probe card and the optical FAU; the ATE comes from the ATE supplier as part of the customer's existing test configuration.

Which test approaches handle optical and electrical access together on dense chips?

Test approaches for dense chips differ, and the table lists each approach with the strengths InZiv lists for it.

Approach	Stated strengths
Active-alignment wafer probers (alignment by measured optical feedback)	Large installed base, long photonics assembly and alignment heritage, single-sided silicon photonics systems already partly deployed, double-sided systems available today, probe-card scale, global service, established ATE integrations
Polymer-lens fiber arrays	Scale, global supply chain, qualification with test-system integrators
In-house probe station with a hexapod	Already paid for, flexible for one-off experiments, familiar to its engineers, fine at low volume
Pass/fail testing at the ports	Costs nothing, changes nothing in the flow, good enough while volumes and yields are acceptable
Established test equipment	Handles electrical and endpoint optical testing well
Passive-alignment wafer test (Glide-SiPh PIC)	Passive alignment without an active fiber search on every device; available to order

A team may reconsider its approach when alignment consumes too much of the device-test cycle, the optical probe cannot reach the coupling interface, or coupling variation makes device results hard to interpret.

How does InZiv's Glide-SiPh PIC handle optical and electrical characterization on a dense PIC?

InZiv's Glide-SiPh PIC handles optical and electrical characterization on a dense PIC while the wafer is whole, with multichannel optical and electrical characterization, optical insertion loss per channel, full-wafer functional pass/fail testing and wafer-level yield and uniformity mapping, per InZiv's product specifications. It uses passive alignment, which is optical positioning by calibrated geometry and wafer registration instead of an optical-feedback search at every device. The FAU is calibrated on a jig and placed on the wafer using fiducials, with no hexapod, no iterative tuning and no optical recalibration between cycles, and alignment takes seconds per device.

InZiv builds three elements of the setup in-house: the prober, the electrical probe card and the optical FAU. The customer's existing ATE, from the ATE supplier, completes the test configuration.

Key optical interface attributes:

Probe type: patented deep-trench FAU, a monolithic fiber array unit, handling both edge-coupled and grating-coupled devices.
Mechanical behavior: the FAU rests on the wafer, keeping optical coupling stable and repeatable during the test.
Wafer formats: per InZiv, Glide-SiPh PIC tests 200 mm and 300 mm wafers and is FOUP compatible.
Automation: wafer handling (EFEM), probe-card replacement and probe alignment.

For design or failure-analysis engineers whose coupling region stays a black box after tape-out, Omni-SiPh LightView is the analysis counterpart, and it is designed to reduce iteration cycles from weeks to hours.

Where in the test flow should in-circuit optical and electrical access be inserted?

Within the test flow, InZiv's intended coverage spans test insertion points 1, 2 and 3: wafer testing before and after bonding, as well as testing of individual dies after wafer dicing.

Insertion point 1, wafer testing before bonding. Engineers establish whether each PIC functions optically and electrically while the wafer is still whole.
Insertion point 2, wafer testing after bonding. Here a PIC is joined to an EIC. Optical interfaces and electrical pads can sit on opposite faces of the stack, so this stage can call for double-sided testing. The question is whether the bonded assembly still meets its optical and electrical specification.
Insertion point 3, testing of individual dies after wafer dicing. Engineers confirm known-good die status, within the coverage and limits of the tests applied, before dies move on.

InZiv's role across these stages is intended coverage. Within the product scope, high-throughput pass/fail sorting and wafer-level yield and uniformity mapping are the job of Glide-SiPh PIC, while imaging light inside the circuit and identifying the root cause of a failure are the job of Omni-SiPh LightView, including offline failure analysis when something goes wrong in production.

What criteria should a test engineer use when evaluating an in-circuit PIC tester?

The criteria a test engineer uses when evaluating an in-circuit PIC tester start from the job the tester must do. In-circuit optical characterization, spatially resolved analysis inside a working circuit where near-field optical probes show where light is lost and why, is the job of Omni-SiPh LightView. Production testing through the device's optical and electrical ports, with full-wafer functional pass/fail testing and high-throughput sorting at volume, is the job of Glide-SiPh PIC. The criteria below act as a checklist rather than a ranking.

Wafer sizes and carrier handling. Confirm the wafer diameters, carrier format and automated loading the prober supports.
Access geometry. Check that the optical probe can reach the coupler types in the design, including edge couplers recessed in trenches and surface grating couplers, and that the electrical probe card can contact the pads.
Optical and electrical measurement set. Specify which optical and electrical characterization runs on each device, such as per-channel insertion loss, the optical power lost along a path, usually expressed in dB.
Repeatability. Establish whether device variation can be separated from coupling variation, since coupling variation makes device results hard to interpret.
Single-sided versus double-sided access. Bonded PIC and EIC stacks can present optical and electrical interfaces on opposite faces, so establish which faces the access method reaches and at which stage of the flow.
ATE integration. Verify how the prober and probe card integrate with your existing ATE and software.
Data for yield work. Ask for per-device records that stay traceable into yield and uniformity maps.

Frequently Asked Questions

What does simultaneous optical and electrical access mean on a dense PIC?

Simultaneous optical and electrical access on a dense PIC means an optical probe couples light into or out of the device while an electrical probe card makes electrical contact with it, so a functional verdict covers both domains. New designs can put edge couplers in trenches too narrow for the current fiber array. In an InZiv Glide-SiPh PIC setup, the prober positions the wafer, the deep-trench FAU provides the optical access and the electrical probe card provides the electrical contact, while the customer's existing ATE supplies electrical stimulus and measurement. Glide-SiPh PIC is available to order.

How does Glide-SiPh PIC's passive alignment position the optical probe?

Passive alignment positions the optical probe using calibrated geometry and wafer registration, without an optical-feedback search at each device. Glide-SiPh PIC calibrates its FAU on a jig and places it on the wafer using fiducials, with no hexapod, no iterative tuning and no optical recalibration between cycles. According to InZiv's Glide-SiPh PIC product specifications, the patented deep-trench FAU is monolithic, supports a pitch down to 30 µm and handles both edge-coupled devices, which take light through an exposed facet, and grating-coupled devices, which take light through a patterned surface structure.

Which InZiv system fits production sorting, and which fits root-cause analysis?

Glide-SiPh PIC is built for production testing and Omni-SiPh LightView for analysis. The two answer different questions about the same wafer.

Criterion	Glide-SiPh PIC	Omni-SiPh LightView
Purpose	High-throughput pass/fail sorting at volume	In-circuit optical characterization and root-cause identification
Optical approach	Passive alignment with a deep-trench FAU, edge and grating coupling	Near-field optical probes mapping light propagation and optical loss inside the circuit
Hardware and probes	Prober, probe card and optical FAU built in-house by InZiv	Near-field, deep-trench and angled probes, plus custom designs for specific architectures
Measurement data	Multichannel optical and electrical characterization, insertion loss per channel, yield and uniformity mapping	IV, LIV and wavelength, at wafer and die level
Typical stage	High-volume production test, with first customer use possible during the NPI ramp	Process development and NPI, design validation, yield debugging, offline failure analysis

Both systems are available to order as of 2026. Where a PIC fails with excess optical loss and standard test equipment measures only the light going in and coming out, Omni-SiPh LightView is designed to reduce iteration cycles from weeks to hours by showing the component where light is lost, such as a bend, a splitter, a coupler or a waveguide section.

What test stages does InZiv's coverage include?

According to InZiv, its intended coverage spans test insertion points 1, 2 and 3: wafer testing before bonding, wafer testing after bonding, and testing of individual dies after wafer dicing. Bonded stacks pair a PIC with an EIC, and such architectures can place optical and electrical interfaces on opposite faces, which is what double-sided testing addresses in general. Per InZiv's Glide-SiPh PIC product specifications, the system tests 200 mm and 300 mm wafers and is FOUP compatible, with automated wafer loading, alignment, probe engagement and stepping. Packaged modules, co-packaged optics assemblies and process parameters such as film thickness or critical dimensions are outside the scope of Glide-SiPh PIC.

When does keeping an existing probe station make sense?

A team may keep its current setup because it meets present measurement and volume requirements, has already passed qualification, or integrates well with its preferred ATE and software. An in-house probe station with a hexapod is already paid for, flexible for one-off experiments, familiar to its engineers and fine at low volume, where an active search per device is slow but tolerable. Teams reconsider when alignment consumes too much of the device-test cycle, when the optical probe cannot reach the coupling interface, when coupling variation makes device results hard to interpret, when production volumes outgrow the setup's automation or throughput, when maintaining a custom system consumes too much engineering, or when a yield problem appears that port data cannot explain. Testing of the finished co-packaged module, and very low-volume labs that need only input/output power measurements, are outside InZiv's fit today.

About this article

InZiv publishes this article under its own name and is responsible for its accuracy. Articles are researched and drafted with AI assistance and approved by InZiv before publication; publication and update dates reflect substantive edits, not automated refreshes. Last updated: 2026-11-01